ANOOP HOSMANI KAREGOWDA
Mob: 9008904283
e-mail:anoophosmani@gmail.com 49, 2nd ward, Basaweshwara Nagara
M B AYYANAHALLI, BALLARI –583126
KARNATAKA, INDIA
Post Applied For : Electro Technical Officer
Career Objective:
Seeking a challenging environment in a leading organization that encourages continuous learning and to endeavor towards achieving vision of the organization through personal improvement and teamwork.
Educational Qualification:
|
Qualification |
Institution |
University |
Year of passing |
Percentage |
|
Mtech(VLSI and Embedded system) |
BNMIT |
Visvevaraya Technological University |
2016 |
74.6% |
|
B.E (Electronics & Communication) |
Bapuji Institute of Engineering & Technology |
Visvevaraya Technological University |
2014 |
60.27% |
|
P.U.C |
SBCJ PU college |
Department of Pre-University Education |
2010 |
54% |
|
S.S.L.C |
Vidya vikas vidya samsthe |
Karnataka Secondary Education Examination Board |
2008 |
76.80% |
DETAILS OF DOCUMENTS:
|
DOCUMENTS |
NO. |
DATE OF ISSUE |
PLACE OF ISSUE |
VALIDITY |
|
PASSPORT |
P3518930 |
25/07/2016 |
BENGALURU |
24/07/2026 |
|
CDC (INDIAN) |
MUM 269192 |
07/01/2017 |
MUMBAI |
06/01/2027 |
|
INDOS NO. |
16LL0277 |
29/08/2016 |
MUMBAI |
|
|
YELLOW FEVER |
|
|
|
|
DETAILS OF COURSE/CERTIFICATE:
|
DOCUMENTS |
Cert NO. |
DATE OF ISSUE |
PLACE OF ISSUE |
|
Pre Sea training Certificate
|
ETO A-I/EMA/5-16/000046
|
15/12/2016 |
ERNAKULAM |
|
PSSR |
PSSR/ETO A-I/EMA/000046
|
05/10/2016 |
ERNAKULAM |
|
PST |
PST/ETO A-I/EMA/5-16/000046
|
01/10/2016 |
ERNAKULAM |
|
FP&PF |
FPFF/ETO A-I/EMA/5-16/000046
|
28/09/2016 |
ERNAKULAM |
|
EFA |
EFA/ETO A-I/EMA/5-16/000046
|
08/10/2016 |
ERNAKULAM |
|
STS |
STS/ETO A-I/EMA/5-16/000046
|
13/10/2016 |
ERNAKULAM |
Technical Skills
Programming Languages C.
Hardware Description Languages Verilog, SystemVerilog.
Interested Topics in VLSI
Logic Design , Scan Insertion, Scan compression, Boundary Scan
VLSI Design/EDA Tools and Simulators
Mentor Questasim, Cadence IC Design tools (Schematic Editor, Virtuoso Layout,) Cadence’s Spectre Simulator, Xilinx FPGA Design Tools , Vi Editor, DFT complier , BSD Compiler ,.
Professional Experience:
Internship at National Aerospace Laboratories, Bengaluru and project at Knoxx technologies,Bengaluru.
Training Experience
Worked on the project “Implementation for SRAM based FPGA correction of Single-bit & Multi-bit Upsets using Embedded Hamming Scheme “
Attended two day “CADENCE “ workshop conducted by BIET College
Attended three day “Embedded Operating Syatems(RTOS) Programming “ workshop conducted by IEEE Bengaluru section.
Achievements:
Published a research paper titled “Implementation of single bit Error detection and Correction using Embedded hamming scheme “ in International Journal of Modern Trends in Engineering & Research (IJMTER)
Participated in Science talent examination.
Bagged many prizes in athletic sports in school & college
Personality Qualities:
Linguistic ability in English, Hindi, Kannada,Telugu.
Inquisitive and industrious and honest.
Ability to work with a team
Personal Profile:
Date of birth : 4th Febraury 1993
Nationality : Indian
Hobbies : Dancing, Reading novels, Badminton
I hereby that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars.
Place:
Date: Your’s faithfully
ANOOP H K